硬件描述语言 第二周 (二选一)

程序代码:

module top;

wire A, SEL, C, D, E ,F ,G;
system_clock #300 clock1(A);
system_clock #150 clock2(SEL);
system_clock #100 clock3(C);

not  a0(D,SEL);
and a1(E, A, SEL);
and a2(F, C, D);
or a3(G ,E , F);

endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;

initial clk=0;

always
 begin
#(PERIOD/2) clk=~clk;
 end

always@(posedge clk)
 if($time>1000)$stop;

endmodule

程序图像：