硬件描述语言第三周 AND (三个输入信号 )

程序代码:module top;

wire A, B, C, D, F;
system_clock #400 clock1(A);
system_clock #200 clock2(B);
system_clock #100 clock3(C);

and a1(D, A, B);
and a2(F, C, D);

endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;

initial clk=0;

always
 begin
#(PERIOD/2) clk=~clk;
 end

always@(posedge clk)
 if($time>1000)$stop;

endmodule