程序代码:
module top;
integer ia[1:0],ib [1:0];integer is;
reg [1:0] a,b;
reg s;
wire [1:0] out;
mux2 mc(out[1:0],a[1:0],b[1:0],s);
initial
for (ia[0]=0; ia[0]<=1; ia[0] = ia[0]+1)begin
a [0]= ia[0];
for (ia[1]=0; ia[1]<=1; ia[1] = ia[1]+1)
begin
a [1]= ia[1];
for (ib[0]=0; ib[0]<=1; ib[0] = ib[0] + 1)
begin
b[0] = ib[0];
for(ib[1]=0; ib[1]<=1; ib[1] = ib[1] + 1)
begin
b[1] = ib[1];
for (is=0; is<=1; is = is + 1)
begin
s = is;
#1 $display("a[0]=%d a[1]=%d b[0]=%d b[1]=%d s=%d out[0]=%d out[1]=%d",a[0],a[1],b[0],b[1],s,out[0],out[1]);
endend
end
end
end
endmodule
module mux2(OUT, A, B, SEL);
output [1:0] OUT;
input [1:0] A,B;
input SEL;
mux_behavioral hi (OUT[1], A[1], B[1], SEL);
mux_behavioral lo (OUT[0], A[0], B[0], SEL);
endmodule
module mux_behavioral(OUT, A, B, SEL);
output OUT;input A,B,SEL;
wire A,B,SEL;
reg OUT;
always @(A or B or SEL)
OUT = (A & SEL)|(B & ~SEL );endmodule

没有评论:
发表评论