程序代码:module top;
integer ia,ib,is,ic,id;reg a0,b0,a1,b1,s;
wire out0,out1;
mux_behavioral mux2(out0,out1,a0,b0,a1,b1,s);
initial
beginfor (ia=0; ia<=1; ia = ia+1)
begin
a0= ia;
for (ib=0; ib<=1; ib = ib + 1)
begin
b0 = ib;
for (is=0; is<=1; is = is + 1)
begin
s = is;
for (ic=0; ic<=1; ic = ic+1)
begina1 = ic;
for (id=0; id<=1; id = id+1)
begin
b1 = id;
#1 $display("a0=%d a1=%d s=%d b0=%d b1=%d out0=%d out1=%d",a0,a1,s,b0,b1,out0,out1);
end
end
endend
end
end
endmodule
module mux_behavioral(OUT0,OUT1, A, B,C,D, SEL);
output OUT0,OUT1;
input A,B,SEL,C,D;wire A,B,SEL,C,D;
reg OUT0,OUT1;
always @(A or B or SEL or C or D )
beginOUT0= (A & ~SEL)|(B & SEL );
OUT1= (C & ~SEL)|(D & SEL );
end
endmodule


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