硬件描述语言----三种模式

程序代码: module top;
wire A, B, Cin, E, F, G, cout, SUM;
system_clock #400 clock1(Cin);
system_clock #200 clock2(B);
system_clock #100 clock3(A);
and a1(E, A, B);
xor a2(F, A, B);
and a3(G, F, Cin);
or  a4(cout,E, G);
xor  a5(SUM, F, Cin);
endmodule
module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial clk=0;
always
 begin
#(PERIOD/2) clk=~clk;
 end
always@(posedge clk)
 if($time>1000)$stop;
endmodule






module top;
  integer ia,ib,ic;
  reg  a,b,cin;
  wire cout,sum;
  and_behavioral and1(cout,sum,a,b,cin);
  initial
    begin
      for (ia=0; ia<=1; ia = ia+1)
        begin
          a = ia;
          for (ib=0; ib<=1; ib = ib + 1)
            begin
              b = ib;
  for (ic=0; ic<=1; ic = ic + 1)
  begin
  cin=ic;
              #1 $display("a=%d b=%d cin=%d cout=%d sum=%d",a,b,cin,cout,sum);
                        end
    end
     end
end
endmodule
module and_behavioral(cout,sum,a,b,cin);
  input a,b,cin;
  output cout,sum;
  wire a,b,cin;
  reg cout,sum;
  always @(a or b or cin)
   begin
    cout  = a&cin|a&b|b&cin;
    sum = ~a&b&~cin|~cin&a&~b|a&b&cin|~a&~b&cin;
   end    
endmodule




module test_adder1;
 reg a,b;
 reg carry_in ;
 wire sum;
 wire carry_out;
 adder1_behavorial A1(carry_out, sum, a, b, carry_in);
 initial
  begin
    carry_in = 0; a = 0; b = 0;
    # 100 if ( carry_out != 0 | sum !== 0)
                $display(" 0+0+0=00 sum is WRONG!");
              else
                $display(" 0+0+0=00 sum is RIGHT!");
   carry_in = 0; a = 0; b = 1;
    # 100 if ( carry_out != 0 | sum !== 1)
                $display(" 0+0+1=01 sum is WRONG!");
              else
                $display(" 0+0+1=01 sum is RIGHT!");
    carry_in = 0; a = 1; b = 0;
    # 100 if ( carry_out != 0 | sum !== 1)
               $display(" 0+1+0=01 sum is WRONG!");
              else
               $display(" 0+1+0=01 sum is RIGHT!");
   carry_in = 0; a = 1; b = 1;
    # 100 if ( carry_out != 1 | sum !== 0)
               $display(" 0+1+1=10 sum is WRONG!");
              else
               $display(" 0+1+1=10 sum is RIGHT!");
   carry_in = 1; a = 0; b = 0;
    # 100 if ( carry_out != 0 | sum !== 1)
               $display(" 1+0+0=01 sum is WRONG!");
              else
               $display(" 1+0+0=01 sum is RIGHT!");
    carry_in = 1; a = 0; b = 1;
    # 100 if ( carry_out != 1 | sum !== 0)
               $display(" 1+0+1=10 sum is WRONG!");
              else
               $display(" 1+0+1=10 sum is RIGHT!");
    carry_in = 1; a = 1; b = 0;
    # 100 if ( carry_out != 1 | sum !== 0)
               $display(" 1+1+0=10 sum is WRONG!");
              else
               $display(" 1+1+0=10 sum is RIGHT!");
    carry_in = 1; a = 1; b = 1;
    # 100 if ( carry_out != 1 | sum !== 1)
               $display(" 1+1+1=11 sum is WRONG!");
              else
               $display(" 1+1+1=11 sum is RIGHT!");
    $finish;
  end
endmodule

module adder1_behavorial (carry_out, sum, a, b, carry_in);
 input a, b, carry_in;
 output carry_out, sum;
  assign sum = (~a&b&~carry_in)|(~carry_in&a&~b)|(a&b&carry_in)|(~a&~b&carry_in);
  assign carry_out = a&carry_in|a&b|b&carry_in;
endmodule

硬件描述语言 ------- 两位元多功能选择器 (第五周)

程序代码:

module top;

  integer ia[1:0],ib [1:0];
  integer is;
  reg [1:0] a,b;
  reg s;
  wire [1:0] out;

 mux2  mc(out[1:0],a[1:0],b[1:0],s);

  initial

    for (ia[0]=0; ia[0]<=1; ia[0] = ia[0]+1)
        begin
          a [0]= ia[0];
  for (ia[1]=0; ia[1]<=1; ia[1] = ia[1]+1)
  begin
  a [1]= ia[1];
            for (ib[0]=0; ib[0]<=1; ib[0] = ib[0] + 1)
    begin
    b[0] = ib[0];
    for(ib[1]=0; ib[1]<=1; ib[1] = ib[1] + 1)
     begin
     b[1] = ib[1];
                   for (is=0; is<=1; is = is + 1)
                   begin
                      s = is;

                     #1 $display("a[0]=%d a[1]=%d b[0]=%d b[1]=%d s=%d   out[0]=%d out[1]=%d",a[0],a[1],b[0],b[1],s,out[0],out[1]);

                    end
                end
           end
     end
  end
endmodule
module mux2(OUT, A, B, SEL);
output [1:0] OUT;
input [1:0] A,B;
input SEL;
mux_behavioral hi (OUT[1], A[1], B[1], SEL);
mux_behavioral lo (OUT[0], A[0], B[0], SEL);
endmodule

module mux_behavioral(OUT, A, B, SEL);

 output OUT;
 input A,B,SEL;
 wire  A,B,SEL;
 reg    OUT;

  always @(A or B or SEL)

   OUT = (A & SEL)|(B & ~SEL );
endmodule

第四周 (二位元选择器) 行为结构

程序代码:module top;

  integer ia,ib,is,ic,id;
  reg  a0,b0,a1,b1,s;
  wire out0,out1;
mux_behavioral mux2(out0,out1,a0,b0,a1,b1,s);

  initial

    begin
      for (ia=0; ia<=1; ia = ia+1)
        begin

          a0= ia;

          for (ib=0; ib<=1; ib = ib + 1)

            begin

              b0 = ib;

              for (is=0; is<=1; is = is + 1)

                begin

                  s = is;

                  for (ic=0; ic<=1; ic = ic+1)

                    begin
                    a1 = ic;
                      for (id=0; id<=1; id = id+1)

                        begin

                        b1 = id;

                 #1 $display("a0=%d a1=%d s=%d b0=%d b1=%d  out0=%d out1=%d",a0,a1,s,b0,b1,out0,out1);

                        end

                    end

                end
            end
         end
      end
endmodule

module mux_behavioral(OUT0,OUT1, A, B,C,D, SEL);

 output OUT0,OUT1;

 input A,B,SEL,C,D;
 wire  A,B,SEL,C,D;
 reg    OUT0,OUT1;

  always @(A or B or SEL or C or D )

  begin
     OUT0= (A & ~SEL)|(B & SEL );
     OUT1= (C & ~SEL)|(D & SEL );
  end
endmodule

硬件描述语言 (第四周) ---------2位多选器

程序代码:module top;

wire A0, A1, B0, B1,SEL,E, D, F, G, H, OUT0, OUT1;
system_clock #1600 clock1(A0);
system_clock #800 clock2(A1);
system_clock #400 clock3(B0);
system_clock #200 clock3(B1);
system_clock #100 clock3(SEL);

not  a0(E,SEL);
and a1(D, A0, E);
and a2(F, B0, SEL);
and a3(G, A1, E);
and a4(H, B1, SEL);
or  a5(OUT0,D,F);
or  a6(OUT1,G,H);
endmodule
module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial clk=0;
always
 begin
#(PERIOD/2) clk=~clk;
 end
always@(posedge clk)
 if($time>2000)$stop;
endmodule

硬件描述语 (第四周 )三个输入信号

硬件描述语言 第二周 (二选一)

程序代码:

module top;

wire A, SEL, C, D, E ,F ,G;
system_clock #300 clock1(A);
system_clock #150 clock2(SEL);
system_clock #100 clock3(C);

not  a0(D,SEL);
and a1(E, A, SEL);
and a2(F, C, D);
or a3(G ,E , F);

endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;

initial clk=0;

always
 begin
#(PERIOD/2) clk=~clk;
 end

always@(posedge clk)
 if($time>1000)$stop;

endmodule

程序图像：

硬件描述语言第三周 AND (三个输入信号 )

程序代码:module top;

wire A, B, C, D, F;
system_clock #400 clock1(A);
system_clock #200 clock2(B);
system_clock #100 clock3(C);

and a1(D, A, B);
and a2(F, C, D);

endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;

initial clk=0;

always
 begin
#(PERIOD/2) clk=~clk;
 end

always@(posedge clk)
 if($time>1000)$stop;

endmodule