wire A0, A1, B0, B1,SEL,E, D, F, G, H, OUT0, OUT1;
system_clock #1600 clock1(A0);
system_clock #800 clock2(A1);
system_clock #400 clock3(B0);
system_clock #200 clock3(B1);
system_clock #100 clock3(SEL);
not a0(E,SEL);
and a1(D, A0, E);
and a2(F, B0, SEL);
and a3(G, A1, E);
and a4(H, B1, SEL);
or a5(OUT0,D,F);
or a6(OUT1,G,H);
endmodule
module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial clk=0;
always
begin
#(PERIOD/2) clk=~clk;
end
always@(posedge clk)
if($time>2000)$stop;
endmodule


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