程序代码：module top;
wire A, B, OUT；
system_clock #400 clock1(A);
system_clock #200 clock2(B);
and a1(OUT, A, B);
endmodule
module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial clk=0;
always
begin
#(PERIOD/2) clk=~clk;
end
always@(posedge clk)
if($time>1000)$stop;
endmodule
